1. Field of the Invention
The present invention relates generally to transistors and, more particularly, to an enhancement mode GaN transistor with reduced gate leakage current between the gate and the 2DEG region.
2. Description of the Related Art
GaN semiconductor devices are increasingly desirable because of their ability to switch at high frequency, to carry large current, and to support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET). These types of devices can typically withstand high voltages, e.g., 30V-to-2000 Volts, while operating at high frequencies, e.g., 100 kHZ-100 GHz.
A GaN HEMT device includes a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer cause the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
The nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because the 2DEG region exists under the gate at zero gate bias, most nitride devices are normally on, or depletion mode devices. If the 2DEG region is depleted (i.e., removed) below the gate at zero applied gate bias, the device can be an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide and because they are easier to control with simple, low cost drive circuits. An enhancement mode device requires a positive bias applied at the gate in order to conduct current.
FIG. 1 illustrates a conventional schematic enhancement-mode GaN transistor. As shown, a p-type material 101 is used as the gate 103. At 0V bias, the p-type material 101 depletes the 2DEG 102 under the gate 103, and the device is in an OFF state. The transistor is turned ON by applying a positive voltage to the gate 103. FIG. 2 illustrates a schematic diagram of two gate leakage current paths 201, 202 of a conventional enhancement-mode GaN transistor. The first gate leakage current path 201 flows along the sidewall of the p-type gate material 101 and the second gate leakage current path 202 flows through the bulk of the p-type gate material 101.
FIGS. 3A and 3B illustrate schematic diagrams of two test structures 300A, 300B designed to determine the types of structures for an enhancement-mode GaN transistor that may result in lower gate leakage current. In particular, the transistor structure 300A illustrated in FIG. 3A is designed with a larger gate surface area and fewer gate edges when compared to the transistor structure 300B illustrated in FIG. 3B. In this example, the transistor structure 300A has a gate surface area of 140,000 μm2 and 2,500 μm edges, while the transistor structure 300B has a gate surface area of 84,000 μm2 and 247,000 μm edges.
FIG. 4 illustrates a graphical comparison of the gate leakage currents of the transistor structures 300A and 300B illustrated in FIG. 3A and 3B, respectively. As shown, structure 300B has a higher gate leakage current than structure 300A, suggesting that the gate leakage current is predominately along the gate edge, i.e., path 201 illustrated in FIG. 2.
Accordingly, it is an object of the present invention is to provide an enhancement-mode GaN transistor with reduced gate leakage current between the gate 103 and the 2DEG 102.